1. Field of the Invention
The invention relates, inter alia, to an integrated circuit arrangement containing a multiplicity of conductive structures which are electrically conductive and which are structured in accordance with a grain structure. Conductive structures made of copper or made of a copper alloy are affected, in particular.
2. Description of Related Art
As minimum feature sizes decrease, a trend toward ever shorter heat treatment times can be observed in semiconductor technology. Both the total of the time for heat treatment operations and the duration of individual heat treatment steps are shortened because sufficient annealing of the material defects or sufficient grain formation already occurs even with short heat treatment operations given small dimensions. RTP methods with a heat treatment time of a few seconds are thus employed.
Interconnects made of copper are usually clad with a barrier material, which preferably does not form an alloy with copper and which constitutes a diffusion barrier for copper atoms against outdiffusion, into the intermetal dielectric or into the substrate. The electrical conductivity of the barrier material is lower than that of the copper. However, the lining increases the stability of the conductive structure against electromigration.
The conductive structures can be subdivided into vias and interconnects. The vias are arranged in insulting layers between two interconnect layers and serve for vertical current transport between the interconnects of different levels. The insulating layer with the vias additionally serves for the capacitive decoupling of interconnects of different levels.